Regviz

Espressif Systems /ESP32-S3 /SYSTEM /CORE_1_CONTROL_0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CORE_1_CONTROL_0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/SYSTEM/CORE_1_CONTROL_0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CONTROL_CORE_1_RUNSTALL)CONTROL_CORE_1_RUNSTALL 0 (CONTROL_CORE_1_CLKGATE_EN)CONTROL_CORE_1_CLKGATE_EN 0 (CONTROL_CORE_1_RESETING)CONTROL_CORE_1_RESETING

Description

Core0 control regiter 0

Fields

CONTROL_CORE_1_RUNSTALL

Set 1 to stall core1
CONTROL_CORE_1_CLKGATE_EN

Set 1 to open core1 clock
CONTROL_CORE_1_RESETING

Set 1 to let core1 reset

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data